The present invention relates to three dimensional metal oxide semiconductor (MOS) technology and, in particular, to vertically integrated or "stacked" CMOSFET structures.
Two of the continuing goals of the microelectronics industry are to increase device packing densities and to enhance performance characteristics such as the speed of operation. The ongoing attempts to scale devices and associated structures have been successful to date in reducing the size and relative spacing between active devices, conductive paths and regions of isolating dielectric, but with some resulting problems caused by, for example, difficulties in photolithographic resolution and device interaction.
Another way to increase MOS device density, besides scaling per se, involves vertical integration, in which devices are stacked one above the other. This approach has significant potential for increased device packing density. In addition, in CMOS technology, the stacked structure can eliminate p-wells, decrease the latch-up phenomenon and provide decreased wire routing complexity.
There are a number of approaches for configuring such stacked MOSFETS For example, a separate gate, stacked CMOS configuration is described in Kawamura et al., "Three-Dimensional CMOS ICs Fabricated Using Beam Recrystallization", IEEE Electron Device Letters, Vol. 4, No. 10, pp. 366-368, 1983. As shown in FIG. 2, this stacked device 26 includes two "upright" transistors, that is, two non-inverted PMOS and NMOS transistors 27 and 28 which have separate gates 29 and 30 as well as separate source-channel-drain structures 31 and 32. The lower, PMOS device 27 is apparently formed using standard silicon technology; then a double layer of phosphosilicate glass (PSG) 33 and nitride 34 is formed as the intermediate insulation layer between the stacked devices. The function of the double insulation layer is to minimize surface undulation and to decrease optical reflection during laser irradiation of the polysilicon channel structure 32. Apparently, the NMOS transistor 28 is formed over the PMOS transistor 27 by depositing a second layer of polysilicon (gate 29 is the first poly layer), which is recrystallized and selectively doped to form the NMOS source-channel-drain structure 32, then depositing a third layer of poly and forming it into the NMOS gate 30.
A vertically and horizontally integrated structure is described in Gibbons et al., "Stacked MOSFETs in a Single Film of Laser-Recrystallized Polysilicon," IEEE Electron Device Letters, Vol. 3, p. 191, 1982. In this structure, two transistors are provided in a cross-shaped single gate configuration. The paired opposite ends of the cross form the source and drain of the two transistors. The upper and lower surfaces of the polysilicon layer at the junctive of the cross serve as the gates for the two transistors.
Stacked CMOS structures which use a single common gate and recrystallized polysilicon for the upper source-channel-drain structure are also described in Chen et al., "Stacked CMOS SRAM Cell," IEEE Electron Device Letters, Vol. 4, p. 272, 1983; and in Colinge et al., "Stacked Transistors CMOS (ST-MOS), an NMOS Technology Modified to CMOS," IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, pp. 585-589, April 1982. Colinge et al. discloses a stacked, common gate CMOS inverter which comprises a conventional lower field effect transistor and an upper PMOS field effect transistor. Colinge et al. uses standard poly NMOS processing to form the lower device. That is, source, drain and self-aligned gate electrode 85 (poly I) are formed in and on the substrate. Then there is added a selectively implanted and laser recrystallized polycrystalline silicon layer, which forms the PMOS source, channel and drain. The PMOS drain contacts the NMOS drain to provide an inverter configuration.
Reviewing the relevant part of the Colinge et al. process in greater detail, after forming the NMOS device, the common gate is oxidized and etched to smooth the upper surface for the formation of the second gate oxide. The PMOS gate oxide is then grown on top of the common gate and the second poly layer (poly II) is deposited and implanted to adjust the threshold voltage of the upper PMOS device. The poly II layer is then selectively capped with an antireflective silicon nitride coating and is recrystallized using a CW argon laser. Subsequently, the poly II channel is masked and the source/drain regions are doped p-type by boron implantation. The structure is then completed by the standard sequence of poly II patterning, oxide caping, contact cuts, aluminum deposition and metal patterning.
It should be noted that the source-channel-drain structure of the upper PMOS device is not self-aligned with the common gate. Consequently, the alignment of the p.sup.+ source-drain implant mask is critical to minimize capacitive coupling between the source/drain regions and the gate electrode.
Finally, Pashley U.S. Pat. No. 4,272,880, discloses a stacked, common gate MOSFET inverter in which the source-channel-drain structure of a lower NMOS device is formed in an epi layer and the source-channel-drain structure of the PMOS device is formed in a layer of recrystallized polysilicon. The totally self-a1igned nonplanar process patterned nitride as an etch mask to define the common gate, then uses the same mask as an implant mask in forming the n-type source and drain. Thereafter, the upper part of the epi layer is oxidized to form an isolation layer over the n-type source and drain with the nitride being retained to mask an underlying gate oxide layer during a p-type implant of the isolation oxide surface. Subsequently, the p-type source and drain are formed by updiffusion from the doped oxide surface so that they are aligned with the common gate.
In short, the Pashley process uses the nitride in accordance with standard silicon self-alignment techniques to patterning and implanting the lower NMOS transistor, then retains the nitride and uses it as a dopant implant mask for the isolation oxide surface so that the p-type source and drain are aligned with the common gate by updiffusion.